Field of the Invention
The present invention relates to an electronic circuit and a camera.
Description of the Related Art
When the distance between signal lines decreases, the parasitic capacitance between the signal lines becomes a problem. Particularly, when signals of opposite phases are output to two adjacent signal lines, signal transition is delayed due to the parasitic capacitance between the two signal lines. Japanese Patent Laid-Open No. 2-284449 discloses an invention with an objective to solve this problem which occurs when signals of opposite phases are output to two adjacent signal lines. Specifically, Japanese Patent Laid-Open No. 2-284449 discloses a semiconductor storage device which includes a first group of signal lines composed of a plurality of signal lines for transmitting in-phase signals and a second group of signal lines composed of a plurality of signal lines for transmitting signals of a phase opposite to that of the first group of signal lines. In this semiconductor device, the distance between the first group of signal lines and the second group of signal lines is greater than the distance between the signal lines within the same group of signal lines.
Such a method which reduces signal transition delays due to parasitic capacitance by increasing the distance between the signal lines, as that disclosed in Japanese Patent Laid-Open No. 2-284449, increases the area occupied by each group of signal lines and leads to an increase in circuit area.